Receiver

ABSTRACT

Receiver comprising a cascade of first to N resonance amplifiers (SA 1 , SA 2 , SA 3 ), an output thereof being coupled to signal processing means (TO, SD, PK, LP 1 , S) for deriving a baseband modulation signal. To improve the signal to noise ratio said cascade is included in an RF input stage of the receiver for a distributed selective amplification of an RF reception signal, preferably with an impedance level of the individual resonance amplifiers within said cascade of first to N resonance amplifiers increasing in signal downstream direction.

[0001] The invention relates to a receiver comprising a cascade of firstto N resonance amplifiers being included in an RF input stage of thereceiver for a distributed amplification of an RF reception signal, anoutput thereof being coupled to signal processing means for deriving abaseband modulation signal. Such receiver is on itself known, e.g. fromthe article “Three-Dimensional Masterslice MMIC on Si Substrate” byToyoda et al, published in IEEE Transactions on Microwave Theory andTechniques, US, IEEE Inc., New York, volume 45, no. 12, Part 02, 1 Dec.1997 (Dec. 12, 1997), pages 2524-2530, XP000732041 ISSN: 0018-9480. Theamplifiers used in this known RF input stage provide distributedamplification of an RF input signal within a wide band frequency rangein the order of magnitude of 6 GHz or more. The use of resonanceamplifiers in a cascade in the IF part of a conventional superhetreceiver concept to selectively amplify an IF signal is on itself knownfrom U.S. Pat. No. 5,220,686. Furthermore, a non-cascaded application ofa plurality of N gain stages in an RF input stage of a radio receiver isknown from WO 99 46855 A (Koninklijke Philips Electronics N.V.; PhilipsA B (SE), published on 16 Sep. 1999. These gain stages do not providedistributed amplification as only one of these gain stages at a time isbeing activated.

[0002] Said cascade of first to N resonance amplifiers is on itselfsuitable for integration. However, the use thereof in a superhetreceiver does not allow for full receiver integration, because of thespecific system architecture of the conventional superhet concept. Theadvantages of fully integrated receiver architectures over conventionalreceiver architectures are known: they will offer a much smallerphysical size and a much lower cost price. Such monolithicallyintegrated receivers are in particular advantageous for use in specificapplications, including clock controlled devices (e.g. radio's in PDAs,lap-tops, GSM, etc). Up to now the performance of these fully integratedreceiver architectures was always lower due to the limitations of thesignal processing properties of active devices compared to the(discrete) passive ones. Important indicators of signal processingperformance are e.g. sensitivity, far-off and channel selectivity,dynamic range and tuning behaviour.

[0003] The cost price of a monolithic integrated receiver is, as of anyIC, a complex quantity being determined a.o. by external components(X-tal, antenna, large time constants), chip area and yield (matching,spread).

[0004] It is a first object of the invention to offer a receiverarchitecture, which can be monolithically integrated.

[0005] It is a second object of the invention optimise theprice/performance ratio of such monolithically integrated receiver.

[0006] It is a third object of the invention to provide measures todecrease the chip area of an integrated receiver without giving in onperformance.

[0007] A receiver comprising a cascade of first to N resonanceamplifiers, an output thereof being coupled to signal processing meansfor deriving a baseband modulation signal, according to the invention istherefore characterised in that said first to N resonance amplifiers inthe cascade providing selective distributed amplification, the impedancelevel of the individual resonance amplifiers within said cascade offirst to N resonance amplifiers increasing in signal downstreamdirection.

[0008] The invention is based on the recognition that with a selectiveRF signal amplification distributed over a number of cascaded resonanceamplifiers, various parameters of the individual resonance amplifiers,such as noise figure and far-off selectivity work out differently on theoverall characteristic of the cascade, dependent on the position of theresonance amplifier in the cascade. The noise figure of the firstresonance amplifier, i.e. the resonance amplifier being first suppliedwith the RF reception signal, has a larger weight in the overall noisefigure of the cascade as a whole than its succeeding or second resonanceamplifier and so forth. On the other hand, the far-off selectivity ofthe first resonance amplifier may be much less, or in other words thebandwidth may be larger, without giving in on the overall far-offselectivity of the cascade as a whole, than the second one, and soforth. By taking this into account when applying distributed RFamplification, an optimised trade-off between said signal parameters canbe obtained allowing for further receiver signal processing withcircuitry, which in itself is very much suitable for integration.

[0009] According to the invention, such optimised trade off is obtainedby increasing the impedance level of the individual resonance amplifierswithin said cascade of first to N resonance amplifiers in signaldownstream direction. This allows for a decreasing scaling factor, i.e.a decrease of the set currents (Ig, It, Ibw) and capacitances C of theresonance amplifiers in the cascade in signal downstream directionwithout affecting the performance compared with the known receiver withidentical stages resulting in a decrease of the chip area needed, whilestrongly reducing the chip area needed.

[0010] A preferred embodiment of a receiver according to the inventionis characterised in that the noise figure of the individual resonanceamplifiers within said cascade of first to N resonance amplifiersdecrease in signal upstream direction. For an implementation of thismeasure, use is made of the recognition that for a selective resonanceamplifier as mentioned above, Vnoise=sqrt(fc/(B*C) in which Vnoiserepresents the noise figure of a resonance amplifier, fc the centerpassband frequency of the resonance amplifier, B the bandwidth and C thecapacitance value of the resonance amplifier and allows for to anoptimised trade off between Vnoise, B and C per each resonance amplifierin the cascade, without affecting the overall noise figure of thecascade as a whole.

[0011] Another preferred embodiment of a receiver according to theinvention optimised in terms of selectivity is characterised in that thebandwidth of the individual resonance amplifiers within said cascade offirst to N resonance amplifiers decrease in signal downstream direction.transconductance amplifiers TC3 and TC4 realise an extra negativeresistor, which can be considered to be arranged parallel to theparallel RC members R1C1 and R2C2, respectively. By applying a fixed setcurrent Ibw to control terminals of TC3 and TC4, the transconductance ofTC3 and TC4 and therewith the bandwidth or selectivity of the resonanceamplifier SA can be set to a predetermined value without affecting itstuning frequency. Fifth and sixth transconductance amplifiers TC5 andTC6 are included between quadrature voltage inputs Vin and V′in of theresonance amplifier SA on the one hand and the above current inputs Iinand I′in of the resonance amplifier SA on the other hand. By supplying again control current Ig to control terminals of TC5 and TC6 the overallgain of the resonance amplifier SA can be varied without affecting theresonance frequency fres and/or the bandwidth of the resonance amplifierSA. In the embodiment shown, the resonance amplifier SA can be used toselectively amplify a pair of phase-quadrature signals, hereinafterreferred to as first amplification mode.

[0012] By mutually coupling the quadrature voltage inputs Vin and V′in,respectively the quadrature voltage outputs Vout and V′out, as shown inFIG. 1b, the resonance amplifier SA can be used to selectively amplify asingle phase input signal into a single phase output signal hereinafterreferred to as second amplification mode.

[0013] By mutually coupling the quadrature voltage inputs Vin and V′inof the resonance amplifier SA, as shown in FIG. 1c, the resonanceamplifier SA selectively amplifies a single phase input signal, whileconverting the same into a pair of phase-quadrature output signals Voutand V′out, this mode of operation of the resonance amplifier SA beinghereinafter referred to as third amplification mode.

[0014] By mutually coupling the quadrature voltage outputs Vout andV′out, the resonance amplifier SA selectively amplifies a pair ofphase-quadrature input signals while converting the same into amon-phase output signal this mode of operation of the resonanceamplifier being hereinafter referred to as fourth amplification mode.

[0015] The description of the resonance amplifier SA given sofar issufficient for a proper understanding of the invention. For moreinformation of the resonance amplifier SA, reference is made to theabove U.S. Pat. No. 5,220,686.

[0016]FIG. 2 shows an embodiment of a receiver according to theinvention comprising a cascade of respectively first to N (N=3)resonance amplifiers SA1, SA2, SA3, hereinafter also referred to as“cascade”, for a selective amplification of an RF reception signal beingsupplied from antenna means ANT to an RF input of the cascade. Each ofthe resonance amplifiers SA1, SA2, SA3 correspond to the one of FIG. 1boperating in the above second amplification mode, however according tothe invention, they differ mutually in their settings with regard to thebandwidth or selectivity and/or their scaling factor or impedance level,such that:

[0017] the bandwidth of SA3 is smaller than the bandwidth of SA2 and thebandwidth of SA2 is smaller the bandwidth of SA1, i.e. the bandwidth ofthe resonance amplifiers SA1, SA2 and SA3 decreases in signal downstreamdirection. Such bandwidth setting is obtained by a proper set value forthe bandwidth set currents Ibw of SA1, SA2 and SA3. The selectivity ofthe resonance amplifiers SA1, SA2 and SA3 therewith increases in signaldownstream direction.

[0018] The bias setpoints or scaling factor of the resonance amplifierSA1 is larger than the bias setpoints or scaling factor of the resonanceamplifier SA2, which in its turn is larger than the bias setpoints orscaling factor of the resonance amplifier SA3. As a result thereof thecapacitance C and therewith the impedance level of SA1, SA2 and SA3increases in signal downstream direction allowing to reduce the chiparea, necessary for an implementation of the cascade, without giving inon the overall noise figure of the cascade.

[0019] Said cascade of first to N resonance amplifiers is coupled tobaseband signal demodulation means comprising a.o. a tuning oscillatorTO providing a pair of phase quadrature oscillator signals fi (0°) andfq (90°), the in-phase oscillator signal fi (0°) being supplied as alocal synchronous RF carrier to a carrier input of the synchronousdetector SD and the quadrature phase oscillator signal fq (90°) beingprovided to a carrier input of the phase detector PD. The tuningoscillator TO is preferably implemented by using a regenerativelyfedback resonance amplifier (not shown). The phase detector PD isincluded in a phase locked loop (PLL) comprising a loop filter LP1coupled between an output of PD and a tuning control input of the tuningoscillator TO. The PLL provides a negative feedback of phase differencesbetween the carrier signal of the selectively amplified output signal ofthe cascade on the one hand and the phase quadrature oscillator signalof TO on the other hand, therewith phase synchronising the pair of phasequadrature oscillator signals to the incoming RF carrier signal. Thetuning oscillator TO is also manually variable to a wanted RF carrierfrequency with a tuning control current It supplied to a tuning controlinput of the tuning oscillator TO. Along with the tuning of TO, thetuning control current It is also supplied to tuning inputs of SA1, SA2and SA3 to secure a mutually parallel tuning between TO on the one handand SA1, SA2 and SA3 on the other hand. Outputs of the synchronousdetector SD and the amplitude detector PK are coupled to first andsecond switching terminals of a switching device S for connecting one ofthose detectors to a common output terminal of the switching device S.Said common switching device output terminal is coupled to basebandmodulation signal processing means, comprising a lowpass filter LP3 forselecting the useful baseband modulation signal, e.g. an audiosignal,from the output signal of the switching device S.

[0020] The switching device S is controlled by an in-lock detector LDbeing coupled between an output of the loop filter LP1 on the one handand a switching control terminal of the switching device S on the otherhand and detecting the in-lock state of the PLL from the level of theoscillator phase control signal in the PLL. The implementation of suchin-lock detector LD lies within the normal abilities of the skilled man,reason for which no further details of the in-lock detector LD is given.The in-lock detector LD controls the switching device S to couple anoutput of the synchronous detector SD to the common output terminal ofthe switching device S when the PLL is locked to a wanted RF carrierfrequency and to couple the amplitude detector PK to said common outputterminal when the PLL is out of lock. If in lock, the output signal ofSD provides a better signal-to-noise ratio than the output signal of PK.If the PLL is out of lock, i.e. fi (0°) is not phase/frequencysynchronised with the RF carrier signal at the output of the cascade,then it is the amplitude detector PK providing a better signal-to-noiseratio than the synchronous detector SD. This secures an optimalreception of the receiver in terms of signal to noise ratio at varyingsignal reception quality.

[0021] The gain distribution of the resonance amplifiers SA1, SA2 andSA3 is chosen to optimise for the noise figure of the cascade as awhole. Preferably, the signal gain per each resonance amplifier SA1, SA2and SA3 is chosen to decrease in signal downstream direction.Furthermore, the receiver shown is provided with an AGC loop, whichincludes the synchronous detector SD being coupled through a lowpassfilter LP2 to an input of gain control signal generating means C. Thegain control signal generating means C derives gain control currentsIg1, Ig2 and Ig3 from the output signal of the lowpass filter LP2 beingsupplied to gain control input terminals of the respective resonanceamplifiers SA1, SA2 and SA3 of the cascade, such that any deviation inthe signal input level of SD (and therewith also any deviation in thesignal input level of PD and PK) from a predetermined set level isnegatively fed back to the gain control input terminals of therespective resonance amplifiers SA1, SA2 and SA3. This results in areduction of such deviations, therewith effecting a stabilisation ofsaid signal input level at said predetermined set level.

[0022] Preferably, the gain factors of the gain control currents Ig1,Ig2 and Ig3 in the AGC loop are chosen to mutually deviate, such that avariation of the RF input signal level causes the gain of the firstresonance amplifier SA1 to vary stronger than the gain of the secondresonance amplifier SA2 and the gain of the second resonance amplifierSA2 to vary stronger than the gain of the third resonance amplifier SA3of the cascade. This measure results in a further improvement of thesignal-to-noise ratio of the cascade, which come in addition to theimpovement in signal-to-noise ratio obtained with the above settings ofSA1, SA2 and SA3.

[0023] The gain control ranges of SA1, SA2 and SA3 are furthermorechosen to be mutually shifted to provide a deferred or delayedamplification in the respective resonance amplifiers at a decrease ofthe received RF signal carrier. Such deferred or delayed amplificationis as such known and is to maximise the overall range of linearamplification of the cascade.

[0024] The implementation of gain control signal generating means Cproviding the above specified functions lies on itself within theability of one skilled in the art.

[0025] The AM-receiver shown in this FIG. 2 is suitable for monolithicintegration and may be used for receiving various different categoriesof broadcasting signals, such as e.g. radio broadcast AM-signals,vestigial sideband television broadcast signals, etc.

[0026]FIG. 3 shows a second embodiment of a receiver according to theinvention in which the first resonance amplifier SA1 in the cascadeoperates in the above third mode of amplification, i.e. the inputs beingcoupled in accordance with the resonance amplifier SA as shown in FIG.1c, and in which the second and third resonance amplifier SA2 and SA3both operate in the above first mode of operation. The antenna means ANTsupply a single phase RF input signal to the input of the firstresonance amplifier SA1, in which it is selectively amplified and phasesplitted in a pair of phase quadrature signals being supplied to a pairof phase quadrature input terminals of the second resonance amplifierSA2. In SA2 a further selective amplification takes place, thequadrature relationship of the pair of phase quadrature signals beingfurther improved by the suppression of non-orthogonal frequencycomponents occurring in the I and Q parts of the filter sections of theresonance amplifier SA2. The pair of phase quadrature signals is againselectively amplified and improved in its quadrature phase relationshipthe third resonance amplifier SA3.

[0027] SA3 supplies the in-phase component I of the so amplified pair ofphase quadrature signals to a signal input of the synchronous detectorSD, and the phase quadrature component Q thereof to a signal input ofthe phase detector PD. The phase detector PD is included in a PLL, whichfurther includes a first lowpass filter LP1, in the loop being followedby a lowpass filter LP4, which provide a tuning control signal to thetuning oscillator TO. The tuning oscillator TO generates a pair of phasequadrature signals fi(0°) and fq(90°), the in-phase oscillatorsignalfi(0°) being supplied to a carrier input of the synchronous detector SD,the phase quadrature oscillatorsignal fq(90°) being supplied to acarrier input of phase detector PD. The PLL of this receiver functionsin accordance with the PLL of the receiver of FIG. 2, in that itprovides a negative feedback of phase differences between the carriersignal of the selectively amplified output signal of the cascade on theone hand and the phase quadrature oscillator signal of TO on the otherhand, therewith phase synchronising the pair of phase quadratureoscillator signals to the incoming RF carrier signal. Unlike thereceiver of FIG. 2, the use of an amplitude detector, an in-lockdetector and a switching device is avoided in the present receiver inthat an output of the synchronous detector SD is followed through alowpass filter LP5 by a first squaring device SQI and an output of thefirst lowpass filter LP1 by a second squaring device SQQ. Outputs ofthese first and second squaring devices SQI and SQQ are coupled to anadder device AD providing an signal addition of the squared componentsI² and Q² of the phase quadrature baseband amplitude modulation signalof the RF input signal, resulting in a detection of said basebandamplitude modulation signal being reflected in v(I²+Q²). Although notstrictly necessary, this baseband amplitude modulation signal mayoptionally be further selected in a lowpass filter LP6 following theadder device AD.

[0028] The output of the adder device AD is fed back to the cascadethrough a second lowpass filter LP2, therewith forming an AGC loop,functioning in accordance with the AGC described with reference to thereceiver of FIG. 2.

[0029] Also this second embodiment of the receiver according to theinvention is suitable for monolithic integration, while providing atleast comparable receiver performance as non-integratable receivers suchas those using the above superhet receiver concept.

[0030]FIG. 4 shows a signal plot demonstrating the increase in signal tonoise ratio or noise figure as a function of the RF signal voltage inputlevel for an existing prior art Philips IC TEA 5551 in curve a, for anexisting prior art Philips IC TEA 5762 in curve b, for a cascade withSA1, SA2 and SA3 having mutually equal bandwidth or selectivity Q=5 incurve c and for a cascade with SA1, SA2 and SA3 having increasingbandwidth or selectivity Q in signal downstream direction according tothe invention: for SA1: Q1=2; for SA2: Q2=5.5 and for SA3: Q3=10 incurve d. The scaling factors or impedance levels of the resonanceamplifiers SA1, SA2 and SA3 in all these cases have been chosen at amutually equal value 1.

[0031] The improvement in signal-to-noise ratio (or sensitivity)resulting from the increase in bandwidth or selectivity in signaldownstream direction appears clearly for RF signal voltage input levelsbelow 50 dBuV.

[0032]FIG. 5 shows a signal plot demonstrating the increase in signal tonoise ratio as a function of the RF signal voltage input level for theabove existing prior art Philips IC TEA 5551 in curve a, for the aboveexisting prior art Philips IC TEA 5762 in curve b, for a cascade withSA1, SA2 and SA3 having respective bandwidth or selectivity values Q1=2;Q2=5 and Q3=10 in signal downstream direction according to the inventionand mutually equal scaling factor or impedance value 1 in curve c andfor a cascade with SA1, SA2 and SA3 having respectively the sameincreasing bandwidth or selectivity values Q1=2; Q2=5.5 and Q3=10 aswell as respective scaling factors or impedance levels SF1=2, SF2=0.75and SF3=0.25 according to the invention in curve d. The improvement insignal to noise ratio obtained with the measure to decrease the scalingfactor or to increase the impedance level for the resonance amplifiersSA1, SA2 and SA3 in the cascade in signal downstream direction comes inaddition to the improvement resulting from the increase in bandwidth ofthe resonance amplifiers SA1, SA2 and SA3 in the cascade in signaldownstream direction, as becomes most clearly apparent for RF signalvoltage input levels below 42 dBuV.

[0033] The person skilled in the art of radio design will recognizefurther policies to be followed within the ambit of the presentinvention, the scope of which has justfully been determined by theappended claims hereinafter. For example, the invention can be used notonly in AM radio and AM vestigial sideband television signals, but inall types of receivers, using a selective RF part. Furthermore, thecascade may include any number of resonance amplifiers, the AGC circuitmay be simplified to control the gain of the resonance amplifiers in thecascade similarly. The fixed setting of the bandwidth of the resonanceamplifiers SA1, SA2 and SA3 in accordance with the invention may berealised electronically by applying a properly chosen fixed set currentIbw to TC3 and TC4 of the respective resonance amplifiers SA1, SA2 andSA3, as described above. However, the noise figure of the resonanceamplifiers SA1, SA2 and SA3 may be further be reduced by leaving out TC3and TC4 and by dimensioning R1C1 and R2C2 in each such resonanceamplifier, such that a bandwidth setting of the resonance amplifiersSA1, SA2 and SA3 is obtained, which is in accordance with the abovechosen selectivities of SA1, SA2 and SA3 according to the invention.Apart from the reduction of the noise figure, this also reduces thecircuit lay out complexity and the necessary chip area of each resonanceamplifier.

1. Receiver comprising a cascade of first to N resonance amplifiers(SA1-SA3) being included in an RF input stage (SA1-SA3, C) of thereceiver for a distributed amplification of an RF reception signal, anoutput thereof being coupled to signal processing means for deriving abaseband modulation signal characterised in that said first to Nresonance amplifiers (SA1-SA3) in the cascade providing selectivedistributed amplification, the impedance level of the individualresonance amplifiers (SA1, SA2, SA3) within said cascade of first to Nresonance amplifiers (SA1-SA3) increasing in signal downstreamdirection.
 2. Receiver according to claim 1, characterised in that thebandwidth of the individual resonance amplifiers (SA1, SA2, SA3) withinsaid cascade of first to N resonance amplifiers (SA1-SA3) decrease insignal downstream direction.
 3. Receiver according to claim 1 or 2,characterised in that the noise figure of the individual resonanceamplifiers (SA1, SA2, SA3) within said cascade of first to N resonanceamplifiers (SA1-SA3) decrease in signal upstream direction.
 4. Receiveraccording to one of claims 1 or 3, characterised by said first to Nresonance amplifiers (SA1-SA3) providing a signal gain per eachresonance amplifier (SA1, SA2, SA3) decreasing in signal downstreamdirection.
 5. Receiver according to one of claims 1 or 4, characterisedby control means included in a gain control loop for controlling thegain of said cascade of N resonance amplifiers (SA1-SA3) to provide again control signal amplification for the respective first to Nresonance amplifiers (SA1-SA3) in the cascade, which decreases in signaldownstream direction.
 6. Receiver according to one of claims 1 to 5comprising a tuning oscillator (TO), characterised in that the tuningoscillator (TO) provides a pair of I and Q oscillator signals, the Isignal being supplied to a synchronous detector (SD) and the Qoscillator signal being provided to a phase detector (PD) included in aphase locked loop (PD, LP1, TO), an output of the synchronous detector(SD) being coupled to a first switching terminal of a controllableswitching device (S), said phase locked loop (PD, LP1, TO) being coupledto an in-lock detector (LD) supplying a switching control signal to aswitching control terminal of said controllable switching device (S) forswitching through the output signal of the synchronous detector (SD) tobaseband modulation signal processing means (LP3) when the phase lockedloop (PD, LP1, TO) is in phase lock with an RF input carrier signal. 7.Receiver according to claim 6, characterised in that the output of thecascade of first to N resonance amplifiers (SA1-SA3) is followed by anamplitude detector (PK), having an output being coupled to a secondswitching terminal of the controllable switching device (S) forswitching through the output signal of the amplitude detector (PK) tosaid baseband modulation signal processing means (LP3) when the phaselocked loop is out of lock.
 8. Receiver according to one of claims 1 to5, characterised by the cascade of first to N resonance amplifiers(SA1-SA3) providing a pair of phase quadrature signals, the in-phasecomponent thereof being supplied to a synchronous detector (SD), thequadrature phase component thereof being supplied to a phase detector(PD) included in a phase locked loop (PD, LP1, LP4, TO), outputs of thesynchronous detector (SD) and the phase detector (PD) being selectivelyrespectively coupled to first and second squaring devices (SQI and SQQ,respectively), outputs of said squaring devices (SQI and SQQ,respectively) being coupled to signal inputs of an adder circuit (AD)having an output followed by baseband modulation processing means (LP6).9. Receiver according to claim 8, characterised in that an output of theadder device (AD) is included in an AGC loop controlling the gain factorof each of the first to N resonance amplifiers (SA1, SA2, SA3) in thecascade.
 10. Receiver according to one of claims 1 to 9, characterisedby said resonance amplifiers (SA1, SA2, SA3) comprising activepoly-phase transconductance filter sections (TC1, R1C1 respectively TC2,R2C2).